Writing · Sole-authored, Cal Poly Pomona · 2024
FPGA Power Consumption Benchmarking
Measuring real power draw across two FPGA development boards — a Nexys A7 and a DE0-Nano — instead of trusting the vendor estimate.
FPGA power estimates come out of vendor tooling as a number with a confidence interval nobody states. For a design headed into a power-constrained system, that number is a starting hypothesis, not an answer.
This work benchmarks consumption across two boards from different vendors — a Digilent Nexys A7 and a Terasic DE0-Nano — so the comparison spans architectures rather than characterizing a single part. Both are built from logic elements of the same general shape: a four-input lookup table paired with a flip-flop, replicated across the fabric.
The interest is in how utilization, clocking and design structure move the total, and in how far the measured figure drifts from the estimate. The motivation is the same one that runs through the edge-AI work: a design that meets timing and misses its power budget has not met its requirements, and discovering that on the bench costs far less than discovering it in the system.