Writing · 2024
FPGA Power Consumption Benchmarking
Measuring where power actually goes in an FPGA fabric built from LUT-and-flip-flop logic elements, rather than trusting the vendor estimate.
Sole-authored, Cal Poly Pomona · 2024
FPGA power estimates come out of vendor tooling as a number with a confidence interval nobody states. For a design going into a power-constrained system, that number is a starting hypothesis rather than an answer.
This benchmarking work looks at consumption across a fabric built from logic elements — typically a four-input LUT paired with a flip-flop — and at how utilisation, clocking and design structure move the total.
The motivation is the same one that runs through the edge-AI work: a design that meets timing and fails its power budget has not met its requirements, and finding that out on the bench is much cheaper than finding it out in the system.